I don’t know if anybody ever did it here before, but here it is! Eimerkettenspeicher-5000, the most CPU inefficient delay effect!
The idea is simple. There’s a BBD algorithm that made the analog delays so cool. BBD stands for the “Bucket brigade device”. To put it simply, it is a chain of capacitors that are sampling the input wave and holds it until recieving a trigger. That basically what S&H does, right? So it works, but it is far from being efficient and i don’t think it could be optimized. But it’s fun!
Very cool, I like such hacky use of modules
Haha, thanks! Btw i’ve found a way to kinda optimize it using Shift registers instead of S&H’s. So Eimerkettenspeicher-6000 is a bit less inefficient!
*it was kinda stupid of me not using the Shift Registers from the beginning, cause what my row of S&H’s is doing was basically a Shift Register’s job. Duh (though a row of Branes modules with loooots of wires looks very satisfying)